Public Deliverables
In this page the TRISTAN public deliverable reports are published and available for download. They are structured in-line with the overall TRISTAN structure:
- WP1 deliverables cover the process of requirements to the TRISTAN IPs;
- WP2 within the TRISTAN project aims to develop innovative and secure low-, mid-end and application-class edge processors based on the RISC-V architecture;
- WP3 aims to develop high-quality hardware peripherals to support RISC-V based systems;
- WP4 concern RISC-V based software developments;
- WP5 in TRISTAN is aimed a development of EDA Tools for RISC-V architectures;
- WP6 are the TRISTAN demonstrators that will integrate the developments of the other work packages;
- WP7 is related to Project Management, Dissemination and Exploitation, as well as trainings for the RISC-V ecosystem.
Note that only the public deliverables are listed on this page, some of these also have a confidential side documents that are not shared. In case you want more information about a specific deliverable report, please feel free to contact us at info@tristan-project.eu
D3.1 Detailed Specifications for RISC-V Peripheral Blocks
The deliverable D3.1: Detailed Specifications for RISC-V Peripheral Blocks presents the design specifications of TRISTAN hardware peripheral IPs based on the design requirements which are provided in D1.1: Initial Requirements and Feedback for Processor and Hardware IPs.
D6.1 Design specifications of demonstrator 5GFEC
Demonstrator 5GFEC_EFPGA aims to showcase an SoC prototype as a test chip which accelerates a well-known 5G forward error correction algorithm on the eFPGA IP (i.e., I:Embedded-fpga), which is developed as part of WP3. The 5GFEC_EFPGA SoC prototype includes other hardware IPs developed as part of TRISTAN such as processor (C:CVE4), bus interconnect (I:AXI) and peripherals (I:SoC), and benefit from the tools developed in TRISTAN such as software development tools (e.g., S:Compiler-evaluation, S:HAL) and EDA framework (e.g., E:Kactus2 generator).
D6.2 Preliminary Demonstrator Integration report
This report highlights the status of the integration of WP6 demonstrators. For each demonstrator the maturity of composing building blocks is assessed and planned dates for subsequent milestones are captured. Block diagrams are shown as well as exhaustive list of building blocks and required tools to operate the demonstrator.
D5.1 EDA Framework for RISC-V
This deliverable aims to provide an overview of the tools and the environments that are currently in development or planned to be developed in WP5 of TRISTAN. Almost all Work Items in WP5 of TRISTAN provide or exploit at least one open-source tool for design exploration, verification, or synthesis. On the TRISTAN Unified Access Page it is possible to find a complete overview of the work items, linked with the respective developed tools and the GitHub repositories.
D7.7 Intermediate Virtual Repository
It describes the Virtual Repository approach that is used to share the Open-Source TRISTAN results with the RISC-V ecosystem.
D1.3 Initial requirements and feedback for SW and EDA Tools
Initial requirements and feedback for SW and EDA Tools contains the results of the collection of requirements on software and EDA tools of the project partners working within the TRISTAN.
D1.2 Initial requirements and architectual map of demonstrators
This deliverable report presents the results from the analysis of requirements and the design specifications providing a first insight on the utilization and validation of the TRISTAN IPs in the project’s demonstrators.
D1.1 Initial requirements and feedback for processor and hardware IPs
The deliverable defines the concept of requirements, illustrates the process adopted for the requirements elicitation, reports the set of requirements collected following this process and provides some statistics on them. The requirements elicitation will be further extended, refined and updated, and the new results of these activities will be presented in Deliverable D1.5