It provides references and descriptions of all the TRISTAN IPs (hardware and software). It serves as a Virtual Repository page, gathering all the information about the TRISTAN repositories, their status, and the TRISTAN partners involved in them. The TRISTAN Unified Access Page acts like a static page, to provide a single access point to all the repositories TRISTAN contribute to. The updates and contributions will be upstreamed in the repository themselves.
Some of the repositories are hosted on the OpenHW Group GitHub forge, some are located on other public pages, and some are closed-source. The diagram below shows how the TRISTAN (and ISOLDE) repositories are organised.
TRISTAN IPs
| Repository | License | Status | Description | |
|---|---|---|---|---|
| CVE2 | Solderpad | In progress | A single-issue 2-stage pipeline embedded class of RISC-V CPUs | |
| RVB / RVP Standard Extensions support for CV32E40P core | Solderpad | In progress | Development of light-weight RISC-V Instruction Set Architecture (ISA) extensions to improve the energy efficiency of low-bit-width mixed-precision integer arithmetic | |
| Extensions to the micro-architecture of CV32E40P core | Solderpad | In progress | ||
| VSRV: Simple 32-bit RISC-V Linux-Capable Core | Solderpad | Released | 32-bit compact RISC-V processor that runs off-the-shelf protocols under latest linux kernel | |
| CVA6 | Solderpad | In progress | A configurable family of RISC-V application/embedded cores targetting FPGA and ASIC technologies | |
| RVV coprocessor for CVA6 | Solderpad | Released | RVV (vector) co-processor for CVA6 with support for low precision integer arithmetic (down to 8-bit vector data types) and multi-precision floating-point operations | |
| Timing Channel Protection | Solderpad | Released | Increasing the security features of CVA6. In particular, it provides support for timing channel protection in CVA6 | |
| UVM env and testbench for the CVA6 core | Solderpad | Finished | UVM environment for the verification of RISC-V cores, supporting a thorough verification of the CVA6 (and other) cores to reach TRL-5 | |
| Compression and decompression of digital waveforms | TBD | In progress | Custom instructions for CV32E40X core to improve the performance of real-time compression and decompression of digital waveforms | |
| TraceUnit | TBD | In progress | Architecture and design of RISC-V Trace IP | |
| Hypervisor | Solderpad | Released | Hypervisor support for CVA6 complying with the RISC-V hypervisor extension specifications | |
| Riviera: RISC-V ISA Extensions for NFC Applications | LA_OPT_NXP Software License | Design and Verification completed | CV-X-IF compliant RISC-V Co-processor for a NFC Receiver decoder custom DSP acceleration |
| Repository | License | Status | Description | |
|---|---|---|---|---|
| TSN-TraceBus | TBD | In progress | A secured transmission trace bus with message, TSN and control flow reconstruction elements | |
| GPIO | Solderpad | In progress | A simple GPIO interface controlled via an APB bus | |
| UART 16750 | Solderpad / LGPL-2.1 | In progress | A UART interface controlled via an APB bus | |
| SPI Master | Solderpad | In progress | An SPI master that is controlled via an AXI bus | |
| HPDcache | Solderpad | In progress | An open-source High-Performance, Multi-requester, Out-of-Order L1 Data Cache for RISC-V cores and accelerators. | |
| CLIC | Apache-2.0 | In progress | Core Local Interrupt Controller (CLIC) is an interrupt controller for RISC-V cores with pre-emptive, low-latency, vectored, priority/level based interrupts. | |
| AXI LLC | Solderpad | Released | A parameterizable and runtime-configurable AXI4-compliant last-level cache (LLC) | |
| AXI | Solderpad | Released | AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication | |
| OBI interconnect | Solderpad | In progress | OBI Components: AHB2OBI Bridge, OBI2AHB Bridge, OBI2APB Bridge, OBI2OBI Bridge, OBI XBAR Bridge | |
| eFPGA | Solderpad | In progress | An embedded FPGA IP to offload certain processor tasks and improve overall system performance | |
| Accelerator for post-quantum cryptography | TBD | In progress | Post-Quantum Cryptographic Accelerator | |
| Low-power IO DMA | Solderpad | In progress | A Low Power IO DMA controller with multi-bank memory access and performance enhancements | |
| Heterogeneous Cluster Interconnect (HCI) | Solderpad | In progress | Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores | |
| Reduced-Precision Matrix Multiplication Engine | Solderpad | In progress | Low-Power Floating-Point Accelerator |
| Repository | License | Status | Description | |
|---|---|---|---|---|
| TimeWeaver | proprietary | Released | TimeWeaver is a hybrid measurement-based timing analysis tool to determine the WCET of safety-critical embedded software. As part of TRISTAN, it has been ported to include support for RISC-V processors using the TRISTAN trace IP. | |
| CompCert | dual licensed (see repository) | In progress | CompCert is a formally-verified optimizing C compiler. As part of TRISTAN, it will be extended to support the HSI (hardware-supported instrumentation) interface of the TRISTAN trace IP. | |
| Yocto for CVA6 | MIT | Released | A linux image for a CVA6-based embedded processor | |
| Setting up Yocto and baremetal debug on CVA6 | Apache-2.0 | Released | Guidance to set up baremetal and Linux-based debug on CVA6 | |
| End-to-end stack for ML software development on embedded RISC-V platforms | Apache-2.0 | In progress | A PyTorch-based library for implementing hardware-aware optimizations of AI models (NAS, pruning, quantization) with lightweight algorithms, and enable their subsequent compilation and deployment onto RISC-V targets. | |
| CMSIS-like Open-Source AI, DSP and compute (e.g. BLAS) libraries | In progress | A set of extensions to the open-source PULP-NN library for accelerating AI workloads on RISC-V-based platforms (mainly but not limited to multi-core clusters). Extensions include kernels for fused depthwise-separable convolutions, attention layers, and N:M sparsity. | ||
| COREV GCC | GPL-2.0, LGPL-2.1, GCC Runtime Library Exception | In progress | The CORE-V GCC repository provides a fork of the GNU Compiler Collection (GCC) tailored for the CORE-V family of open-source RISC-V processor cores. It includes custom enhancements and optimizations to support CORE-V-specific architectural features and instructions. The fork provides the compiler backend support for the low-precision and mixed-precision extensions designed in TRISTAN. | |
| COREV Binutils | GPL-2.0, GNU Library General Public License, version 2.0 | In progress | The CORE-V binutils repository contains a customized version of the GNU binutils suite designed for the CORE-V family of RISC-V processor cores. It includes tools like the assembler, linker, and related utilities, enhanced to support CORE-V-specific instruction sets and architectural extensions. The fork adds the binary support required to assemble the low-precision and mixed-precision instructions in the TRISTAN extensions. | |
| ELinOS embedded Linux for RISC-V | GPL | Released | ELinOS is an Embedded Linux distribution and industrial grade Linux with the user-friendly CODEO IDE to build state-of-the-art embedded solutions in a time-saving and cost-efficient manner; also dedicated support from SYSGO is available. ELinOS has strong focus on Security with container support and services, providing drivers, connectivity stacks, real-time extensions and support for industrial hardware (e.g. since long ARM, x86, PowerPC, and, since 2024, RISC-V). | |
| PikeOS CVA-6 support | Proprietary | Released | CVA6 is a 6-stage, single-issue, in-order CPU which implements the 64-bit RISC-V instruction set. PikeOS is a portable real-time operating system based on a separation kernel designed for the highest levels of Safety & Security. The PikeOS technology is certifiable by various certification standards including DO-178C, ECSS, EN 50128 / EN 50657, IEC 61508, and ISO 26262. We plan to support CVA-6 for PikeOS. | |
| LLVM TD from ADL | BSD-2-Clause | In progress | Generate LLVM target description file for RV32 architectures and corresponding instruction encoding, instruction scheduling model, assembler relocation tests automatically generated from an architectural description language (ADL). | |
| Cloud Connector | GPL | Released | Device Client is a group of software modules that run on JamaicaAMS. It securely connects to the Cloud (aicas EDP) to get device status and configuration information, and operates the configuration and OSGi bundle lifecycle on RISC-V devices. It contains several components that were customized for this project. | |
| Device Client | GPL | In progress | Cloud Connector is a software module that runs on JamaicaAMS and is used to exchange data with the cloud (customized aicas EDG) via the MQTT protocol. It is compatible with the OSGi specification and leverages the realtime capabilities of JamaicaAMS. It was newly developed by aicas for this project. | |
| RISC-V Runtime | Apache-2.0 | In progress | A SDK that uses the MPFR as its backend has been delivered to experiment with variable precision in applications. | |
| VxP Tools and Libraries | Apache-2.0 | In progress | A subset of the GNU binutils v2.34 and v2.38 has been enhanced to support encoding/decoding of the RISC-V ISA extension for VXP. |
| Repository | License | Status | Description | |
|---|---|---|---|---|
| Renode | MIT | Released | Simulation Framework | |
| ETISS | BSD-3-Clause | Released | Extendible Translating Instruction Set Simulator | |
| SCC | Apache-2.0 | Released | SystemC Components | |
| PySysC | Apache-2.0 | Released | Python bindings for SystemC | |
| Core DSL | Apache-2.0 | Released | Language to describe ISAs for ISS generation and HLS of RTL implementation | |
| DBT-RISE & DBT-RISE-RISCV | Apache-2.0 | Released | Dynamic Binary Translation - Retargetable ISS Environment Application of CoreDSL & DBT-RISE for RISCV | |
| Verilator | LGPL-3.0 | Released | RTL verification (simulation, formal) Co-simulation with Renode | |
| Questa Verify Property App | Proprietary | Released | Formal verification solutions for RISC-V (OneSpin) | |
| Yosys | ISC License | Released | Open Synthesis Suite | |
| Catapult | Proprietary | Released | High-Level Synthesis and verification suite | |
| Kactus2 | GPL-2.0 | Released | IP-XACT/Kactus2 generator for the Renode simulator platform | |
| Codasip Studio | Proprietary | Released | Tool suite to develop/customize RISC-V IPs | |
| GVSOC | Apache-2.0 | Released | RISC-V Platform Simulator | |
| Messy | Apache-2.0 | In progress | Multi-layer Extra-functional Simulator using SYstemC | |
| Plinio | Apache-2.0 | In progress | A PyTorch-based library for implementing hardware-aware optimizations of AI models (NAS, pruning, quantization) with lightweight algorithms, and enable their subsequent compilation and deployment onto RISC-V targets. | |
| MATCH | Apache-2.0 | In progress | A TVM-based AI compiler for hardware-aware deployment of AI models onto heterogeneous RISC-V targets. | |
| Spike | BSD-3-Clause | Released | RISC-V ISA simulator | |
| VPTOOL | Solderpad | Released | Graphical editor of a Design Verification Plan | |
| SoCDSL | TBD (in progress) | In progress | Automated composition and optimization of compute-intensive SoCs from abstract high-level descriptions | |
| cv_dv_utils | Apache-2.0 | In progress | UVM verification environment for OpenHW cores | |
| Co-processor Generator Tool | TBD (in progress) | In progress | Tool to generate CV-X-IF compliant co-processors based on user definition of operations/instructions. | |
| SUNRISE | TBD (in progress) | in progress | Scalable UNified Restful Infrasructure for System Evaluation. | |
| kMLeon | Proprietary | Released | ML-based tool for the automatic generation of extra-functional models (e.g. performance, power). | |
| uArchiFI | Mozilla Public License | Released | Formal tool for analyzing the robustness of embedded systems against fault injection attacks by combining the RTL of a processor, the binary of a software, and an attacker model. | |
| k-FRP | Apache-2.0 | Released | Formal tool for analyzing the robustness of HW countermeasures to secure embedded systems against fault injection attacks. Optional step within µArchiFI |