It provides references and descriptions of all the TRISTAN IPs (hardware and software). It serves as a Virtual Repository page, gathering all the information about the TRISTAN repositories, their status, and the TRISTAN partners involved in them. The TRISTAN Unified Access Page acts like a static page, to provide a single access point to all the repositories TRISTAN contribute to. The updates and contributions will be upstreamed in the repository themselves.

Some of the repositories are hosted on the OpenHW Group GitHub forge, some are located on other public pages, and some are closed-source. The diagram below shows how the TRISTAN (and ISOLDE) repositories are organised.

TRISTAN IPs

NameLicenseStatusDescription
CVE2SolderpadReleasedA single-issue 2-stage pipeline embedded class of RISC-V CPUs
RVB / RVP Standard Extensions support for CV32E40P coreSolderpadIn progressDevelopment of light-weight RISC-V Instruction Set Architecture (ISA) extensions to improve the energy efficiency of low-bit-width mixed-precision integer arithmetic
Extensions to the micro-architecture of CV32E40P coreSolderpadIn progress
VSRV: Simple 32-bit RISC-V Linux-Capable CoreSolderpadReleased32-bit compact RISC-V processor that runs off-the-shelf protocols under latest linux kernel
CVA6SolderpadReleasedA configurable family of RISC-V application/embedded cores targetting FPGA and ASIC technologies
RVV coprocessor for CVA6SolderpadReleasedRVV (vector) co-processor for CVA6 with support for low precision integer arithmetic (down to 8-bit vector data types) and multi-precision floating-point operations
Timing Channel ProtectionSolderpadReleasedIncreasing the security features of CVA6. In particular, it provides support for timing channel protection in CVA6
UVM env and testbench for the CVA6 coreSolderpadFinishedUVM environment for the verification of RISC-V cores, supporting a thorough verification of the CVA6 (and other) cores to reach TRL-5
Compression and decompression of digital waveformsTBDFinishedCustom instructions for CV32E40X / CV32A60X cores to improve the performance of real-time compression and decompression of digital waveforms.
C-TraceCERN-OHL-SDoneArchitecture and design of RISC-V Trace IP
HypervisorSolderpadReleasedHypervisor support for CVA6 complying with the RISC-V hypervisor extension specifications
Riviera: RISC-V ISA Extensions for NFC ApplicationsLA_OPT_NXP Software LicenseDesign and Verification completedCV-X-IF compliant RISC-V Co-processor for a NFC Receiver decoder custom DSP acceleration
SCAIE-V custom instruction interface for CVA6Apache 2.0ReleasedSCAIE-V is a portable and scalable hardware interface for easily adding custom instructions to processors ranging from microcontrollers to application-level cores
NameLicenseStatusDescription
TSN-Trace-LinkSolderpadReleasedA secured transmission trace bus with message, TSN and control flow reconstruction elements
GPIOSolderpadFinishedA simple GPIO interface controlled via an APB bus
UART 16750Solderpad / LGPL-2.1FinishedA UART interface controlled via an APB bus
SPI MasterSolderpadFinishedAn SPI master that is controlled via an AXI bus
HPDcacheSolderpadFinishedAn open-source High-Performance, Multi-requester, Out-of-Order L1 Data Cache for RISC-V cores and accelerators.
CLICApache-2.0ReleasedCore Local Interrupt Controller (CLIC) is an interrupt controller for RISC-V cores with pre-emptive, low-latency, vectored, priority/level based interrupts.
AXI LLCSolderpadReleasedA parameterizable and runtime-configurable AXI4-compliant last-level cache (LLC)
AXISolderpadReleasedAXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
OBI interconnectSolderpadFinishedOBI Components: AHB2OBI Bridge, OBI2AHB Bridge, OBI2APB Bridge, OBI2OBI Bridge, OBI XBAR Bridge
eFPGASolderpadReleasedAn embedded FPGA IP to offload certain processor tasks and improve overall system performance
Keccak Accelerator for Post-Quantum EncryptionApache-2.0FinishedPost-Quantum Cryptographic Accelerator
Low-power IO DMASolderpadIn progressA Low Power IO DMA controller with multi-bank memory access and performance enhancements
Heterogeneous Cluster Interconnect (HCI)SolderpadIn progressHeterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
Reduced-Precision Matrix Multiplication EngineSolderpadIn progressLow-Power Floating-Point Accelerator
SPEDEApache-2.0 WITH SHL-2.1FinishedHigh-speed serializer/deserializer for synchronization and conversion between serial bitstreams and bytes.
NameLicenseStatusDescription
RenodeMITReleasedRenode is a development framework created by Antmicro, that accelerates hardware product development by letting users simulate complete, complex hardware systems - including both the CPU, peripherals, sensors, environment and wired or wireless medium between nodes. Renode supports hundreds of embedded platforms and comes with a range of developer-oriented features such as state saving and replaying, advanced hooks and events, comprehensive tracing, multi-core debugging, etc.
TimeWeaverproprietaryReleasedTimeWeaver is a hybrid measurement-based timing analysis tool to determine the WCET of safety-critical embedded software. As part of TRISTAN, it has been ported to include support for RISC-V processors using the TRISTAN trace IP.
LLVM TD from ADLBSD-2-ClauseReleasedGenerate LLVM target description file for RV32 architectures and corresponding instruction encoding, instruction scheduling model, assembler relocation tests automatically generated from an architectural description language (ADL).
GCC Toolchain for mixed-precision ISA extensionsGPL2ReleasedSupport of the VPFloat ISA into GCC/Binutils
COREV GCCGPL-2.0, LGPL-2.1, GCC Runtime Library ExceptionReleasedThe CORE-V GCC repository provides a fork of the GNU Compiler Collection (GCC) tailored for the CORE-V family of open-source RISC-V processor cores. It includes custom enhancements and optimizations to support CORE-V-specific architectural features and instructions. The fork provides the compiler backend support for the low-precision and mixed-precision extensions designed in TRISTAN.
COREV BinutilsGPL-2.0, GNU Library General Public License, version 2.0ReleasedThe CORE-V binutils repository contains a customized version of the GNU binutils suite designed for the CORE-V family of RISC-V processor cores. It includes tools like the assembler, linker, and related utilities, enhanced to support CORE-V-specific instruction sets and architectural extensions. The fork adds the binary support required to assemble the low-precision and mixed-precision instructions in the TRISTAN extensions.
GCC/Binutils for VPFloat ISAGPL2ReleasedTimeWeaver is a hybrid measurement-based timing analysis tool to determine the WCET of safety-critical embedded software. As part of TRISTAN, it has been ported to include support for RISC-V processors using the TRISTAN trace IP.
VxP Tools and LibrariesApache-2.0ReleasedA subset of the GNU binutils v2.34 and v2.38 has been enhanced to support encoding/decoding of the RISC-V ISA extension for VXP.
CompCertdual licensed (see repository)ReleasedCompCert is a formally-verified optimizing C compiler. As part of TRISTAN, it is extended to support the HSI (hardware-supported instrumentation) interface of the TRISTAN trace IP.
Support of VPFloat datatypes in the C languageApache 2.0ReleasedThe VPSDK (Variable Precision Software Development Kit) is a C/C++ library developed by CEA, offering software interfaces for variable precision computations. It includes VPFloat for scalar values, VBLAS for inear algebra routines, and VPSolver for computation kernels, enabling precise numerical calculations across arious applications.
ZephyrApache 2.0ReleasedThe Zephyr Project is a scalable real-time operating system (RTOS) supporting multiple hardware architectures, optimized for resource constrained devices, and built with security in mind.
PikeOS CVA-6 supportProprietaryReleasedCVA6 is a 6-stage, single-issue, in-order CPU which implements the 64-bit RISC-V instruction set. PikeOS is a portable real-time operating system based on a separation kernel designed for the highest levels of Safety & Security. The PikeOS technology is certifiable by various certification standards including DO-178C, ECSS, EN 50128 / EN 50657, IEC 61508, and ISO 26262. We plan to support CVA-6 for PikeOS.
Yocto for CVA6MITReleasedA linux image for a CVA6-based embedded processor
Setting up Yocto and baremetal debug on CVA6Apache-2.0ReleasedGuidance to set up baremetal and Linux-based debug on CVA6
ELinOS embedded Linux for RISC-VGPLReleasedELinOS is an Embedded Linux distribution and industrial grade Linux with the user-friendly CODEO IDE to build state-of-the-art embedded solutions in a time-saving and cost-efficient manner; also dedicated support from SYSGO is available. ELinOS has strong focus on Security with container support and services, providing drivers, connectivity stacks, real-time extensions and support for industrial hardware (e.g. since long ARM, x86, PowerPC, and, since 2024, RISC-V).
Debug support for CVA6Apache-2.0ReleasedThis tutorial was developed to help developers debug CVA6, either in bare-metal or under Linux
Cloud ConnectorGPLReleasedCloud Connector is a software module that runs on JamaicaAMS and is used to exchange data with the cloud (customized aicas EDG) via the MQTT protocol. It is compatible with the OSGi specification and leverages the realtime capabilities of JamaicaAMS. It was newly developed by aicas for this project.
Depthwise separable convolution fusionReleasedKernels for GAP8 implementing the layer fusion of depthwise convolution and pointwise convolutions.
Pulp-NN-sparseReleasedKernels for weight sparsity
CMSIS-like Open-Source AI, DSP and compute (e.g. BLAS) librariesReleasedA set of extensions to the open-source PULP-NN library for accelerating AI workloads on RISC-V-based platforms (mainly but not limited to multi-core clusters). Extensions include kernels for fused depthwise-separable convolutions, attention layers, and N:M sparsity.
RISC-V RuntimeApache-2.0ReleasedA SDK that uses the MPFR as its backend has been delivered to experiment with variable precision in applications.
End-to-end stack for ML software development on embedded RISC-V platformsApache-2.0ReleasedA PyTorch-based library for implementing hardware-aware optimizations of AI models (NAS, pruning, quantization) with lightweight algorithms, and enable their subsequent compilation and deployment onto RISC-V targets.
RISC-V support for RTICApache 2.0ReleasedRTIC is a framework used to deploy hard real-time applications scheduled under Stack Resource Policy. The framework finds utility in safety-critical systems where bounded real-time task latency needs to be guaranteed on lightweight embedded systems.
KenningApache-2.0ReleasedKenning, developed and maintained by Antmicro, is an open-source ML framework for creating deployment flows and runtimes for Deep Neural Network applications across a broad spectrum of target hardware. Kenning offers an API for deploying deep learning applications on edge devices by leveraging various model training and compilation frameworks. The framework can be used to build larger, portable edge AI applications.
Device ClientGPLReleasedDevice Client is a group of software modules that run on JamaicaAMS. It securely connects to the Cloud (aicas EDP) to get device status and configuration information, and operates the configuration and OSGi bundle lifecycle on RISC-V devices. It contains several components that were customized for this project.
NameLicenseStatusDescription
KeelhaulApache-2.01ReleasedTool to generate executable, memory-mapped I/O verification test cases from IP-XACT or CMSIS-SVD files.
PlinioApache-2.0ReleasedA PyTorch-based library for implementing hardware-aware optimizations of AI models (NAS, pruning, quantization) with lightweight algorithms, and enable their subsequent compilation and deployment onto RISC-V targets.
MATCHApache-2.0ReleasedA TVM-based AI compiler for hardware-aware deployment of AI models onto heterogeneous RISC-V targets.
RenodeMITReleasedSimulation Framework
ETISSBSD-3-ClauseReleasedExtendible Translating Instruction Set Simulator
SCCApache-2.0ReleasedSystemC Components
PySysCApache-2.0ReleasedPython bindings for SystemC
Core DSLApache-2.0ReleasedLanguage to describe ISAs for ISS generation and HLS of RTL implementation​​
DBT-RISE & DBT-RISE-RISCVApache-2.0ReleasedDynamic Binary Translation - Retargetable ISS Environment​​ Application of CoreDSL & DBT-RISE for RISCV​​
VerilatorLGPL-3.0ReleasedRTL verification (simulation, formal)​ Co-simulation with Renode​​
Questa Verify Property AppProprietaryReleasedFormal verification solutions for RISC-V (OneSpin)​​
YosysISC LicenseReleasedOpen Synthesis Suite​​​
CatapultProprietaryReleasedHigh-Level Synthesis and verification suite​​​
Kactus2GPL-2.0ReleasedIP-XACT/Kactus2 generator for the Renode simulator platform​​​
Codasip StudioProprietaryReleasedTool suite to develop/customize RISC-V IPs​​​
GVSOCApache-2.0ReleasedRISC-V Platform Simulator​
MessyApache-2.0ReleasedMulti-layer Extra-functional Simulator using SYstemC​
SpikeBSD-3-ClauseReleasedRISC-V ISA simulator​
VPTOOLSolderpadReleasedGraphical editor of a Design Verification Plan ​
SoCSmithApache 2.0In progress (documentation currently being written, release planned later in 2026).Automated composition and optimization of compute-intensive SoCs from abstract high-level descriptions​ ​
CORE-V-VERIFApache-2.0ReleasedUVM functional verification environment for the OpenHW CORE-V family of RISC-V cores.
Co-processor Generator ToolTool: LGPL v2.1ReleasedTool to generate CV-X-IF and RoCC compliant co-processors based on user definition of operations/instructions.
SUNRISEApache-2.0ReleasedScalable UNified Restful Infrasructure for System Evaluation.
kMLeonProprietaryReleasedML-based tool for the automatic generation of extra-functional models (e.g. performance, power).
uArchiFIMozilla Public LicenseReleasedFormal tool for analyzing the robustness of embedded systems against fault injection attacks by combining the RTL of a processor, the binary of a software, and an attacker model.
k-FRPApache-2.0ReleasedFormal tool for analyzing the robustness of HW countermeasures to secure embedded systems against fault injection attacks. Optional step within µArchiFI
CV-VeriGenSolderpadReleasedUVM SystemVerilog RISC-V CPU model for functional verification of custom ISA (support for CV-X-IF)

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The TRISTAN project, nr. 101095947 is supported by Chips Joint Undertaking (CHIPS-JU) and its members Austria, Belgium, Bulgaria, Croatia, Cyprus, Czechia, Germany, Denmark, Estonia, Greece, Spain, Finland, France, Hungary, Ireland, Iceland, Italy, Lithuania, Luxembourg, Latvia, Malta, Netherlands, Norway, Poland, Portugal, Romania, Sweden, Slovenia, Slovakia, Turkey.

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