Publications

A collaborative project, TRISTAN aims to advance the ecosystem of RISC-V. Here, you’ll find a comprehensive collection of research outputs, reports, articles, and findings that reflect our commitment to innovation, interdisciplinary research, and the dissemination of knowledge.

Presentations

Watch recent TRISTAN presentations from consortium partners

Scientific Papers

Browse TRISTAN research from academia and industry

News & Updates

See TRISTAN in the media, from news to blogs

TRISTAN Presentations

Europe’s Silicon Comeback: Maturing RISC-V with TRISTAN and OpenHW

Watch this insightful session on the future of open-source RISC-V cores and how collaborative European projects like TRISTAN are driving innovation across the continent.

Open Sourcing Project Sparrow

Learn how Project Sparrow is enabling new AI-driven use cases from ML algorithms to final system deployment (leveraging RISC-V), while reducing system design optimization time, and accelerating the adoption of Sparrow through community collaboration.

TRISTAN: Together for RISC-V Technology and Applications

Patrick Pype, Director Strategic Partnerships, NXP Semiconductors explains how TRISTAN aims to expand, mature and industrialize the European RISC-V ecosystem to compete with existing commercial alternatives.

How can Europe engage more in RISC-V?

RISC-V can foster innovation, enhance technological sovereignty, and stimulate economic growth across Europe. This panel explores the opportunities and challenges that Europe faces in adopting RISC-V, and discusses strategies to promote the widespread adoption of RISC-V within the region.

Scientific Publications

Browse research from TRISTAN consortium partners across academia and industry

Title
Fully Automatic Compiler Retargeting and CV-X-IF Hardware Interface Generation for RISC-V Custom Instructions
Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions
EMSA5: A RISC-V Processor System for Enhanced Functional Safety in Embedded Applications
RedMulE-FT: A Reconfigurable Fault-Tolerant Matrix Multiplication Engine
Determining Worst-Case Execution Time Bounds for Multi-Core Processors
fence.t.s: Closing Timing Channels in High-Performance Out-of-Order Cores through ISA-Supported Temporal Partitioning
Towards modularity of the Rust RTIC real-time scheduling framework
Achieving 100% Code Coverage in Embedded Systems Integration Testing. A Systematic Approach in Embedded Systems Integration Testing
Hardware architecture for CRYSTALS-Kyber post-quantum cryptographic SHA-3 primitives
Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space
Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In
RISC-V: Potenziale eines offenen Standards für Chipentwicklung
Enhancing Neural Architecture Search with Multiple Hardware Constraints for Deep Learning Model Deployment on Tiny IoT Devices
PLiNIO: A User-Friendly Library of Gradient-based Methods for Complexity-aware DNN Optimization
Yun: An Open-Source, 64-Bit RISC-V-Based Vector Processor with Multi-Precision Integer and Floating-Point Support in 65-nm CMOS
Achieving Complete Structural Test Coverage in Embedded Systems Using Trace-Based Monitoring (Short Paper)
An Enhanced Fault Injection Framework for FPGA-Based Soft-Cores
SeTHet - Sending Tuned numbers over DMA onto Heterogeneous clusters: an automated precision tuning story
Neutron Beam Evaluation of Probabilistic Data Structure-based Online Checkers
Lightweight Instrumentation for Accurate Performance Monitoring in RTOSes
Neutron Radiation Tests of the NEORV32 RISC-V SoC on Flash-Based FPGAs
An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds?
Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures
Preventing Soft Errors and Hardware Trojans in RISC-V Cores
CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers
VSRV1: Simple 32-bit Linux RISC-V Core
EMSA5: A RISC-V Processor System for Enhanced Functional Safety in Embedded Applications