It provides references and descriptions of all the TRISTAN IPs (hardware and software). It serves as a Virtual Repository page, gathering all the information about the TRISTAN repositories, their status, and the TRISTAN partners involved in them. The TRISTAN Unified Access Page acts like a static page, to provide a single access point to all the repositories TRISTAN contribute to. The updates and contributions will be upstreamed in the repository themselves.

Some of the repositories are hosted on the OpenHW Group GitHub forge, some are located on other public pages, and some are closed-source. The diagram below shows how the TRISTAN (and ISOLDE) repositories are organised.

TRISTAN IPs

NameLicenseStatusDescription
CVE2SolderpadIn progressA single-issue 2-stage pipeline embedded class of RISC-V CPUs
RVB / RVP Standard Extensions support for CV32E40P coreSolderpadIn progressDevelopment of light-weight RISC-V Instruction Set Architecture (ISA) extensions to improve the energy efficiency of low-bit-width mixed-precision integer arithmetic
Extensions to the micro-architecture of CV32E40P coreSolderpadIn progress
VSRV: Simple 32-bit RISC-V Linux-Capable CoreSolderpadReleased32-bit compact RISC-V processor that runs off-the-shelf protocols under latest linux kernel
CVA6SolderpadIn progressA configurable family of RISC-V application/embedded cores targetting FPGA and ASIC technologies
RVV coprocessor for CVA6SolderpadReleasedRVV (vector) co-processor for CVA6 with support for low precision integer arithmetic (down to 8-bit vector data types) and multi-precision floating-point operations
Timing Channel ProtectionSolderpadReleasedIncreasing the security features of CVA6. In particular, it provides support for timing channel protection in CVA6
UVM env and testbench for the CVA6 coreSolderpadFinishedUVM environment for the verification of RISC-V cores, supporting a thorough verification of the CVA6 (and other) cores to reach TRL-5
Compression and decompression of digital waveformsTBDIn progressCustom instructions for CV32E40X core to improve the performance of real-time compression and decompression of digital waveforms 
TraceUnitTBDIn progressArchitecture and design of RISC-V Trace IP
HypervisorSolderpadReleasedHypervisor support for CVA6 complying with the RISC-V hypervisor extension specifications
Riviera: RISC-V ISA Extensions for NFC ApplicationsLA_OPT_NXP Software LicenseDesign and Verification completedCV-X-IF compliant RISC-V Co-processor for a NFC Receiver decoder custom DSP acceleration
SCAIE-V custom instruction interface for CVA6Apache 2.0In progressSCAIE-V is a portable and scalable hardware interface for easily adding custom instructions to processors ranging from microcontrollers to application-level cores
NameLicenseStatusDescription
TSN-TraceBusTBDIn progressA secured transmission trace bus with message, TSN and control flow reconstruction elements
GPIOSolderpadIn progressA simple GPIO interface controlled via an APB bus
UART 16750Solderpad / LGPL-2.1In progressA UART interface controlled via an APB bus
SPI MasterSolderpadIn progressAn SPI master that is controlled via an AXI bus
HPDcacheSolderpadIn progressAn open-source High-Performance, Multi-requester, Out-of-Order L1 Data Cache for RISC-V cores and accelerators.
CLICApache-2.0In progressCore Local Interrupt Controller (CLIC) is an interrupt controller for RISC-V cores with pre-emptive, low-latency, vectored, priority/level based interrupts.
AXI LLCSolderpadReleasedA parameterizable and runtime-configurable AXI4-compliant last-level cache (LLC)
AXISolderpadReleasedAXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
OBI interconnectSolderpadIn progressOBI Components: AHB2OBI Bridge, OBI2AHB Bridge, OBI2APB Bridge, OBI2OBI Bridge, OBI XBAR Bridge
eFPGASolderpadIn progressAn embedded FPGA IP to offload certain processor tasks and improve overall system performance
Accelerator for post-quantum cryptographyTBDIn progressPost-Quantum Cryptographic Accelerator
Low-power IO DMASolderpadIn progressA Low Power IO DMA controller with multi-bank memory access and performance enhancements
Heterogeneous Cluster Interconnect (HCI)SolderpadIn progressHeterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
Reduced-Precision Matrix Multiplication EngineSolderpadIn progressLow-Power Floating-Point Accelerator
NameLicenseStatusDescription
TimeWeaverproprietaryReleasedTimeWeaver is a hybrid measurement-based timing analysis tool to determine the WCET of safety-critical embedded software. As part of TRISTAN, it has been ported to include support for RISC-V processors using the TRISTAN trace IP.
CompCertdual licensed (see repository)In progressCompCert is a formally-verified optimizing C compiler. As part of TRISTAN, it will be extended to support the HSI (hardware-supported instrumentation) interface of the TRISTAN trace IP.
Yocto for CVA6MITReleasedA linux image for a CVA6-based embedded processor
Setting up Yocto and baremetal debug on CVA6Apache-2.0ReleasedGuidance to set up baremetal and Linux-based debug on CVA6
End-to-end stack for ML software development on embedded RISC-V platformsApache-2.0In progressA PyTorch-based library for implementing hardware-aware optimizations of AI models (NAS, pruning, quantization) with lightweight algorithms, and enable their subsequent compilation and deployment onto RISC-V targets.
CMSIS-like Open-Source AI, DSP and compute (e.g. BLAS) librariesIn progressA set of extensions to the open-source PULP-NN library for accelerating AI workloads on RISC-V-based platforms (mainly but not limited to multi-core clusters). Extensions include kernels for fused depthwise-separable convolutions, attention layers, and N:M sparsity.
COREV GCCGPL-2.0, LGPL-2.1, GCC Runtime Library ExceptionIn progressThe CORE-V GCC repository provides a fork of the GNU Compiler Collection (GCC) tailored for the CORE-V family of open-source RISC-V processor cores. It includes custom enhancements and optimizations to support CORE-V-specific architectural features and instructions. The fork provides the compiler backend support for the low-precision and mixed-precision extensions designed in TRISTAN.
COREV BinutilsGPL-2.0, GNU Library General Public License, version 2.0In progressThe CORE-V binutils repository contains a customized version of the GNU binutils suite designed for the CORE-V family of RISC-V processor cores. It includes tools like the assembler, linker, and related utilities, enhanced to support CORE-V-specific instruction sets and architectural extensions. The fork adds the binary support required to assemble the low-precision and mixed-precision instructions in the TRISTAN extensions.
ELinOS embedded Linux for RISC-VGPLReleasedELinOS is an Embedded Linux distribution and industrial grade Linux with the user-friendly CODEO IDE to build state-of-the-art embedded solutions in a time-saving and cost-efficient manner; also dedicated support from SYSGO is available. ELinOS has strong focus on Security with container support and services, providing drivers, connectivity stacks, real-time extensions and support for industrial hardware (e.g. since long ARM, x86, PowerPC, and, since 2024, RISC-V).
PikeOS CVA-6 supportProprietaryReleasedCVA6 is a 6-stage, single-issue, in-order CPU which implements the 64-bit RISC-V instruction set. PikeOS is a portable real-time operating system based on a separation kernel designed for the highest levels of Safety & Security. The PikeOS technology is certifiable by various certification standards including DO-178C, ECSS, EN 50128 / EN 50657, IEC 61508, and ISO 26262. We plan to support CVA-6 for PikeOS.
LLVM TD from ADLBSD-2-ClauseIn progressGenerate LLVM target description file for RV32 architectures and corresponding instruction encoding, instruction scheduling model, assembler relocation tests automatically generated from an architectural description language (ADL).
Cloud ConnectorGPLReleasedDevice Client is a group of software modules that run on JamaicaAMS. It securely connects to the Cloud (aicas EDP) to get device status and configuration information, and operates the configuration and OSGi bundle lifecycle on RISC-V devices. It contains several components that were customized for this project.
Device ClientGPLIn progressCloud Connector is a software module that runs on JamaicaAMS and is used to exchange data with the cloud (customized aicas EDG) via the MQTT protocol. It is compatible with the OSGi specification and leverages the realtime capabilities of JamaicaAMS. It was newly developed by aicas for this project.
RISC-V RuntimeApache-2.0In progressA SDK that uses the MPFR as its backend has been delivered to experiment with variable precision in applications.
VxP Tools and LibrariesApache-2.0In progressA subset of the GNU binutils v2.34 and v2.38 has been enhanced to support encoding/decoding of the RISC-V ISA extension for VXP.
NameLicenseStatusDescription
RenodeMITReleasedSimulation Framework
ETISSBSD-3-ClauseReleasedExtendible Translating Instruction Set Simulator
SCCApache-2.0ReleasedSystemC Components
PySysCApache-2.0ReleasedPython bindings for SystemC
Core DSLApache-2.0ReleasedLanguage to describe ISAs for ISS generation and HLS of RTL implementation​​
DBT-RISE & DBT-RISE-RISCVApache-2.0ReleasedDynamic Binary Translation - Retargetable ISS Environment​​ Application of CoreDSL & DBT-RISE for RISCV​​
VerilatorLGPL-3.0ReleasedRTL verification (simulation, formal)​ Co-simulation with Renode​​
Questa Verify Property AppProprietaryReleasedFormal verification solutions for RISC-V (OneSpin)​​
YosysISC LicenseReleasedOpen Synthesis Suite​​​
CatapultProprietaryReleasedHigh-Level Synthesis and verification suite​​​
Kactus2GPL-2.0ReleasedIP-XACT/Kactus2 generator for the Renode simulator platform​​​
Codasip StudioProprietaryReleasedTool suite to develop/customize RISC-V IPs​​​
GVSOCApache-2.0ReleasedRISC-V Platform Simulator​
MessyApache-2.0In progressMulti-layer Extra-functional Simulator using SYstemC​
PlinioApache-2.0In progressA PyTorch-based library for implementing hardware-aware optimizations of AI models (NAS, pruning, quantization) with lightweight algorithms, and enable their subsequent compilation and deployment onto RISC-V targets.
MATCHApache-2.0In progressA TVM-based AI compiler for hardware-aware deployment of AI models onto heterogeneous RISC-V targets.
SpikeBSD-3-ClauseReleasedRISC-V ISA simulator​
VPTOOLSolderpadReleasedGraphical editor of a Design Verification Plan ​
SoCDSL (SoCSmith)TBD (permissive planned)In progressAutomated composition and optimization of compute-intensive SoCs from abstract high-level descriptions​ ​
cv_dv_utilsApache-2.0In progressUVM verification environment for OpenHW cores
Co-processor Generator ToolTBD (in progress)In progressTool to generate CV-X-IF compliant co-processors based on user definition of operations/instructions.
SUNRISEApache-2.0ReleasedScalable UNified Restful Infrasructure for System Evaluation.
kMLeonProprietaryReleasedML-based tool for the automatic generation of extra-functional models (e.g. performance, power).
uArchiFIMozilla Public LicenseReleasedFormal tool for analyzing the robustness of embedded systems against fault injection attacks by combining the RTL of a processor, the binary of a software, and an attacker model.
k-FRPApache-2.0ReleasedFormal tool for analyzing the robustness of HW countermeasures to secure embedded systems against fault injection attacks. Optional step within µArchiFI
CV-VeriGenTBD (in progress)In progressUVM SystemVerilog RISC-V CPU model for functional verification of custom ISA (support for CV-X-IF)

Subscribe to our newsletter

SUBSCRIBE

The TRISTAN project, nr. 101095947 is supported by Chips Joint Undertaking (CHIPS-JU) and its members Austria, Belgium, Bulgaria, Croatia, Cyprus, Czechia, Germany, Denmark, Estonia, Greece, Spain, Finland, France, Hungary, Ireland, Israel, Iceland, Italy, Lithuania, Luxembourg, Latvia, Malta, Netherlands, Norway, Poland, Portugal, Romania, Sweden, Slovenia, Slovakia, Turkey.

© TRISTAN. All rights reserved.

Privacy Policy | Terms of Use